Electrical decoder



July 31, 1962 M. J. COLEMAN 3,047,854

ELECTRICAL DECODER Filed Dec. 30, 1958 DIGITAL T0 SHAFT DIGITAL SERVO ANALOG SERVO MOTOR DIGITIZER 1 ERROR 45 44 45 INPUT 2 FIXED AC REFERENCE VOLTAGE 15 1,;

0 1 o l o FIG.| l A l2 SIGN LO BINARY INPUT *3 INFORMATION INVENTOR.

mum/2 J. 0025mm ATTORNEY Unite States The present invention generally relates to an electrical decoder and in particular it relates to a new and improved means for converting binary electricalinformation to an A.C. analog electrical voltage.

In the field of electronic digital computers, the output information from the digital computer must usually be converted into an analog quantity before it may be utilized as readout information orfunction as a control quantity. Means for converting electrical binary information to electricalanalog information areknown in the art, and two generalizedapproaches are utilized for that purpose. One of these. approaches is broadly categorized as voltage summingand the other is known broadly as current summing. ,Each of these approaches has advantages when used in particular environments. However, when itis desired. that the. analog output be in the form of an A.C.,voltage. havingan amplitude equal to the magnitude of the analog and a phase which is indica tive of the sign of the analog, -these..above-identified generalized approaches become undesirable because of the degree of circuit complication that is necessary.

Accordingly, the present-invention describes a means for taking a fixed A.C. voltage sourceand applying this voltage through a variable A.C.. voltage attenuator which attenuates the A.C. voltage of. the, source by an amount which is dependentupon the condition of electronic D.C. switching circuitry which is in turn. determined by the electrical binary information ,to be converted. The variable A.C. voltage attenuator may consist of an A.C. voltage divider having a fixed impedance portion and a selectively variable impedance portion serially connected at the junction at which it is desired to derive the analog A.C. voltage. Moreover, the variable impedance portion may comprise a variable number of plural parallel impedance. paths, as determined by the condition of the aforementioned switching circuitry.

It is, therefore, a primary object of the present invention to provide a new and improved means for converting binary electrical information to an A.C. analog electrical voltage.

It is an additional object of the present invention to provide a new and improved means for converting binary electrical information to an A.C. electrical analog voltage having an amplitude equal to the magnitude of the analog and a phase which is determined by the sign of the analog.

It is another object of the present invention to provide a new and improved means for converting binary electrical information to an A.C. analog electrical voltage utilizing a variable A.C. voltage attenuator having an attenuation which is dependent upon the binary electrical information to be converted. a

It is still another object ofthe present invention to provide a new and improved means for converting binary electrical information to an A.C. analog electrical voltage which comprises anA.C. reference voltage applied to an A.C. voltage divider having a fixed and variable impedance portion. 7

Other objects of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings which disclose, by way of examples, the principle of the invention and the best mode which has been contemplated of applying that principle.

In the drawings:

atent the fixed and variable portions which is controlled FIG. 1 shows an electrical schematic of the teachings of the present invention applied to the conversion of binary electrical information having two orders of binary significance; and

FIG. 2 shows an electrical block diagram of a conventional digital servo system having a digital-to-analog conversion stage in which the electrical schematic of FIG. 1 may be utilized.

Referring to FIG. 1, there are shownthree switching devices comprising, by way of illustration, conventional electrical latch circuits forv storing the binary electrical information to be converted. Specifically, latch. 10 may be utilized to store the sign, latch 11 may be utilized to store the first order of signifiacnce and latch 12 may be utilized to store the second, order of significance of the binary electrical information to be converted.

Considering negative logic, latches 11 and 12 may be minal while in a reset condition corresponding to a binary 0 in their input. Similarly, latches 11 and 12 may be designed to have a down'voltage level at their 1 output terminal and an up voltage level at their 0 output terminal while in a set condition corresponding to a binary 1 in their input. The'l outputpterminal of latches 11 and 12are shown connected to diodes D1 and D2, respectively, through resistances 13 and 1 4, respectively, in order to alter the A.C.. empedance of the variable .A.C.attenuat0r to be described hereinafter, in'accordance with the condition of these latches corresponding to their binary electrical input information. Furthermore, the 0 output terminals of latches 11 and 12 areshown connected to diodes D5 and D6, respectively, so as to provide means for assuring that no'A.C. analog voltage exists when both latches are receiving a binary 0* corresponding to a decimal one.

Referring again to FIG. 1, a fixed A.C. reference voltage is applied to terminal 15 and adi-rect current isolation means comprising capacitor 16 and resistance 17 connected to ground. This specific type of direct currentisolation means forms no part of the present invention as it might alternately have comprised a transformer with one of the terminals of the secondary connected to ground.

According to the present invention, this A.C. reference voltage may then be applied to a variable A.C. voltage attenuator consisting of an A.C. voltage divider having a fixed impedance portion shown as resistance 18 and aselectively variable impedance portion shown including the two parallel impedance paths containing D1 and D2-and the inputimpedance of transistor Q1. As will more fully be described hereinafter, transistor Q1 is being utilized to providea phase change in accordance withbinary sign input information.

his the A.C. voltage amplitude at junction 19 between by the latches 11 and 12 through D1 and D2 in accordance with binary electrical input information. In order to assure that junction 19 is at a positive voltage level, it is connected, as. shown to a +D.C. supply voltage through res1stance'20which forms part of the variable A.C. im-

pedance portion. The part of the variable A.C. imped ance portion including D1 comprises aseries circuit of resistance .Z1,.'D1 and resistance'13 connected between junction 19 and the 1 output terminal of latclr'll. While output terminal of latch 12. Furthermore, in order to provide a better control of the biasing conditions of the diodes, the. common terminal of-the resistance 21 and D1 isgrounded through resistance 23and'the. common terminal of resistance 22 and D2 is grounded through resistance 24 as shown.

Accordingly, when both latches 11 and 12 are in their reset condition corresponding to a binary input information equal to (having a decimal equivalent of zero), the 1 output terminal of each will be at an up voltage level so as to forwardly bias both D1 and D2. Under these conditions, the variable A.C. impedance portion will have its smallest magnitude and the amplitude of the A.C. voltage at junction 19 will be the least. On the ther hand, when latch 11 goes to its set condition and latch 12 remains in its reset condition corresponding to binary input information equal to 01 (having a decimal equivalent of one), the 1 output terminal of latch 11 goes to a down level and the 1 output terminal of latch 12 remains at an up voltage level so that only D2 remains forwardly biased. Accordingly, the magnitude of the variable A.C. impedance portion will increase and the amplitude of the A.C. voltage at junction 19 will be larger representing a decimal one.

Similarly, when latch 11 remains in the reset condition and latch 12 goes to the set condition corresponding to binary input information equal to (having a decimal equivalent of two), the 1 output terminal of latch 11 remains at the up voltage level and the 1 output terminal of latch 12 goes to the down voltage level so that D1 is forwardly biased, while D2 is not. Accordingly and based on proper scaling, if the resistances associated with D2 is greater in relation with the other resistance values within the variable A.C. impedance portion of the A.C. voltage divider, the amplitude of the A.C. voltage at junction 19'wil1 be still larger representing a decimal two.

Likewise, when both latches 11 and 12 are driven to their set condition, both D1 and D2 will no longer be forwardly biased, and the magnitude of the variable A.C. impedance portion will be further increased so that the amplitude at junction 19 will also be increased corresponding to a binary input equal to 11 (having a decimal eqivalent of three).

The A.C. voltage appearing at junction 19 under the input conditions just described may not be completely representative of the analog quantity until it is passed through transistor Q1 to obtain a phase which is indicative of the sign of the binary input information. Q1 is shown as comprising an NPN transistor connected in a common emitter phase splitting configuration. As shown, resistance 25 acts to provide the collector load energized by the +D.C. voltage supply; resistance 26 provides the emitter load; and resistance 27 provides a bias to the base. Resistance 29 is part of the input impedance of Q1 and capacitance 28 acts to isolate direct current therefrom.

The output voltage from Q1 may be taken from either its collector or its emitter. When the output voltage is taken from the emitter, it is in phase with the input signal being applied to the base. On the other hand, when the output voltage is taken from the collector, it is 180 degrees out of phase with the input signal being applied to the base. The collector is connected to output terminal 30 through diode D3, oriented as shown, and the emitter is connected to output terminal 30 through diode D4, oriented as shown. When the 0 output terminal of sign latch 10 is at an up level, D3 is forwardly biased and D4 is back biased. Terminal 30 is connected to the collector of Q1. Similarly, when the 0 output terminal is at a down voltage level, terminal 30 is connected to the emitter of Q1.

The A.C. voltage appearing at terminal 30 is applied to the base of transistor Q2 through resistance 31 and capacitance '32. Transistor Q2, which is shown connected in a common emitter configuration, has an output transformer 33 connected to its collector. Although Q2 and related circuit components may act to isolate the output from the phase changing components, its main function is to prevent any A.C. voltage from passing to the output when latches 11 and 12 are both in a reset condition corresponding to a binary input equal to 00 and a decimal equivalent of zero. To obtain this type of operation, the base-emitter junction of Q2 is maintained in a slightly back biased condition by the proper selection of the biasing resistances 34, 35 and 36. Accordingly, when the voltage level at the base of Q2 is not modified by the application of an up voltage level thereto through either D5 or D6, Q2 remains in a cut oil condition and no A.C. voltage is passed therethrough. Neither D5 and D6 receive an up voltage level from latch 11 or 12 when the binary input information equals a 00 and decimal equivalent of one.

The following are typical circuit components, parameters and voltages which may be utilized in the circuit of FIG. 1 to obtain A.C. voltages of 0, .0 75, .150 and .525 volts r.m.s. to represent binary input information of 00," O1, 10 and 11, respectively:

Fixed A.C. reference voltage 1.78 volts r.m.s. D.C. supply voltage 10 volts D.C. Up voltage level for latches 10 volts. Down voltage level for latches 0 volts. Transistors Q1 and Q2 2N167. Diodes D1, D2, D3, D4, D5, D6 1Nl91. Capacitance 16 1y. farad. Resistance 17 5K ohms. Resistance 18 50K ohms. Resistance 21 6.2K ohms. Resistance 23 3.6K ohms. Resistance 13 3K ohms. Resistance 22 1.8K ohms. Resistance 14 3K ohms. Resistance 24 3.6K ohms. Resistance 20 123K ohms. Capacitance 28 .10 farad. Resistance 29 42K ohms. Resistance 27 200K ohms. Resistance 26 2K ohms. Resistance 25 2.1K ohms. Resistance 40 68K ohms. Resistance 31 62K ohms. Capacitance 32- 1,u farad. Resistance 39 43K ohms. Resistance 37 75K ohms. Capacitance 38 1n farad. Resistance 34 50K ohms. Resistance 35 ohms. Resistance 36 620 ohms.

In general, the selection of these circuit component parameters and voltages is a matter of design to provide the desired scaling required by the particular engineering application. However, the amplitude of the fixed A.C. reference voltage should be small enough so that diodes D1 and D2 are never driven to conduction thereby when the 1 output terminals of latches 11 and 12 are at the down voltage level or stop conducting when the 1 output terminals of latches 11 and 12 are at the up voltage level. Moreover, resistances 23, 13, 14 and 24 should be chosen to produce minimum transit voltages and, while at the same time, allow diodes D1 and D2 to modify the variable A.C. impedance of the A.C. voltage divider as described hereinabove. Furthermore, resistance 37 and capacitor 38 should be selected so as to coact with capacitor 32 and resistance 31 to provide a short turn-off time for transistor Q2.

As described, FIG. 1 shows a new and improved means for converting binary electrical information having two orders of binary significance into an A.C. analog voltage having an amplitude equal to the magnitude of the analog and a phase which is determined by the sign of the analog. Such a conversion means may be utilized to provide the digital-to-analog conversion step within a conventional digital servo system such as that shown in FIG. 2. Re

ferring to FIG. 2, conventionally a digital input quantity is compared with a digital follow-up quantity within a digital comparator 41 so as to provide an error digital quantity which is applied to an electronic digital-to-anaiog converter '42. Converter 42 in turn applies the analog error quantity to a servo amplifier 43 so as to appropriately energize a servo motor 44 for rotation at a velocity commensurate with the magnitude of the error and in a direction determined by the sign of the error. Finally, if an analog-to-digital converter 45, conventionally known as a shaft digitizer, is driven by shaft 46 of servo motor 44, a digital follow-up signal may be derived for application to digital comparator 41 in a manner so as to be equal and opposite to the digital input thereto and null out the error quantity being derived. When the digitalto-analog converter 42 is constructed according to the teachings set forth hereinabove in connection with FIG. 1, an improved performance of the total digital servo system is attained because of the improved time response within the digital-to-analog converter.

While the teachings of the present invention have been described as providing for the conversion of digital information having two binary orders of significance, the same technique could be similarly applied to provide for the conversion of digital information having three or more orders of binary significance.

Referring again to FIG. 1, although the switching components utilized to find the binary information to be converted are shown as latches, it is emphasized that any other conventional bistable switching components could be substituted therefor. In addition, while FIG. 1 has been described based upon the binary electrical information being divided according to negative logic, it should be clear that the circuitry could be modified to operate according to positive logic without departing from the teachings of the present invention.

While there have been shown and described and pointed out the fundamental novel features of the invention as applied to a preferred embodiment along with several specific modifications, it will be understood that many additional omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art, without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims:

What is claimed is:

1. A digital-to-analog converter comprising an A.C. voltage source, a capacitor, a resistor, said capacitor and resistor being connected in series with the A.C. voltage source, electronic D.C. switching means including unidirectional devices responsive to the digital information to be converted, a variable A.C. voltage attenuator providing an attenuation which is dependent on the condition of said D.C. switching means, said variable A.C. voltage attenuator being connected to the common junction of said capacitor and resistor so as to provide a variable A.C. out put voltage at the terminal of said capacitor remote from said common junction, said output voltage having an amplitude commensurate with the analog of said digital information to be converted.

2. A digital-to-analog converter comprising a source of binary electrical information to be converted, D.C. switching means responsive to said binary electrical information, an A.C. voltage reference source, a DC. isolation means connected thereto including an impedance to ground, a first resistance and a second resistance connected in series with one extremity of said series connection being connected to the terminal of said impedance within said D.C. isolation means which is remote from ground, the other extremity of said series connection being connected to a DC. Voltage source, a selectively variable impedance network connected between said common junction of said first and second resistances and A.C. ground, the magnitude of said variable impedance being controlled by said D.C. switching means in response to said binary electrical information to be converted, electronic switching means having on and off switching modes of operation connected to be responsive to the AC. voltage amplitude at said common junction of said first and second resistances, said switching means being responsive to said D.C. switching means so as to be in its closed switch mode only when said binary input information corresponds to a decimal number of other than zero, said A.C. analog output voltage being measured at the output of said switching means.

3. The digital-to-analog converter as set forth in claim 2 wherein said variable impedance network comprises plural parallel resistance paths wherein the voltage at a point within each path is modified in accordance with the binary information stored in said D.C. switching means so that the A.C. voltage amplitude at said common junction of said first and second resistances is modified in accordance therewith.

References Cited in the file of this patent 

